9th International Conference on ICT for Sustainable Development

Authors - Spoorti Patil, Suhas Shirol, Saroja V S, Vijay H M, Rajeshwari M
Abstract - The study introduces a groundbreaking 4x4 reversible gate named "TSG," capable of functioning as a standalone reversible full adder, which simplifies the implementation process by reducing the need for multiple gates. This TSG gate employs two novel approaches: the parallel generation of partial products through Fredkin gates with a delay ('d'), and the reduction of addition steps to log2N using a reversible parallel adder composed of TSG gates. The 4x4 reversible multiplier utilizing these TSG gates outperforms existing designs by reducing the number of reversible gates required and minimizing the generation of non-functional, or garbage, outputs. This advancement highlights the importance of efficient multiplier architectures in improving processor and computing machine performance, with significant implications for low-power CMOS, quantum computing, nanotechnology, and optical computing, thereby suggesting its potential to revolutionize the efficiency of microcontrollers and digital signal processors.