9th International Conference on ICT for Sustainable Development

Authors - Bakkesh V A, Suhas Shirol, Saroja V S, Vijay H M, Rajeshwari M
Abstract - Complex integrated circuits (ICs) are becoming more and more prevalent in a wide range of applications due to the ongoing development and integration of semiconductor technology, which highlights the necessity for trustworthy testing procedures to guarantee IC functionality. Techniques are known as Built-In Self-Test (BIST) have become a viable option for testing these integrated circuits (ICs) both during the manufacturing process and in the field. The pseudo-random pattern generator (PRPG), one of the essential parts of BIST, is essential for creating test patterns that identify circuitry flaws. A Pseudo Random Pattern Generator designed especially for Low Power BIST applications is proposed in this project. The design prioritizes power consumption optimization while preserving the fundamental properties of fault coverage and unpredictability required for thorough testing. Test efficacy and power efficiency are balanced in the suggested PRPG by employing practical algorithms and circuit-level improvements. The architecture is crafted to reduce power consumption without compromising the quality of generated test patterns. By utilizing methods like selective feedback, state encoding, and clock gating, the generator significantly reduces power consumption in comparison to traditional designs.